Semiconductor wafers are often evaluated to identify flatness defects. Flatness defects of a wafer are defined as deviations of a front side of the wafer relative to a specified reference plane when the back surface of the wafer is ideally flat, such as when pulled down by a vacuum onto an ideally clean, flat chuck.
Typically, the front side of the wafer will be divided into equally sized sites prior to the analysis of the flatness of the surface. The flatness of each site is then evaluated using assorted methods. In an SFQR-type method (site flatness, least-squares reference plane), the flatness of an individual site on the front side of the wafer is measured against a least squares, best fit reference plane. For each site, the maximum and minimum deviations from the reference plane are calculated. Another method for evaluating that flatness of the wafer surface is SBIR (site flatness, back side referenced indicator runout). In SBIR-type methods, the reference plane is the ideally flat back surface of the wafer. The maximum and minimum deviations on the front side of the wafer for each site from the back surface of the wafer are calculated. The range of deviations calculated in the analysis of the flatness of the wafer are often used when evaluating the suitability of the wafer for down-stream applications (e.g., lithography or device fabrication).